DESIGN AND IMPLEMENTATION OF HARDWARE ACCELERATORS FOR EMBEDDED AI

The primary objective of this thesis work is to create and develop an automated hardware generation technique capable of producing multiple and distinct implementations of a given modified version of a binarized neural network (BNN), all tailored for FPGA deployment. The fundamental architecture of the generator is discussed, followed by a presentation of the characteristics of each inferred network, ranging from fully parallel solutions that trade hardware utilization for lower execution times to more resource-efficient implementations that conserve hardware space at the expense of slower performance. Samples from the MNIST dataset are used to validate the aforementioned characteristics. This approach to hardware generation aims at creating efficient hardware solutions that are both versatile, to better suit specific user requirements, and extendable to support new design ideas. Overall, the results shown here provide a solid foundation for further research and optimization in the field of automated FPGA development for AI-based applications.