FPGAs offer a highly efficient, parallel, and reconfigurable alternative to CPUs and GPUs for real-time, power-constrained neural network inference, requiring careful hardware optimization. This thesis explores the use of FPGAs for accelerating neural network inference, emphasizing their ad-vantages in real-time and power-constrained applications. It presents the de-sign and implementation of an FPGA-based hardware pipeline for real-time image processing, using a lightweight neural network for color recognition on an Intel DE1-SoC FPGA. The study optimizes the model through quantization techniques, reducing computational overhead while maintaining accuracy. The proposed methodology provides a structured approach to deploying ma-chine learning models on FPGAs, demonstrating low-latency inference and energy efficiency, making it suitable for applications in computer vision, ro-botics, and IoT.
FPGAs offer a highly efficient, parallel, and reconfigurable alternative to CPUs and GPUs for real-time, power-constrained neural network inference, requiring careful hardware optimization. This thesis explores the use of FPGAs for accelerating neural network inference, emphasizing their ad-vantages in real-time and power-constrained applications. It presents the de-sign and implementation of an FPGA-based hardware pipeline for real-time image processing, using a lightweight neural network for color recognition on an Intel DE1-SoC FPGA. The study optimizes the model through quantization techniques, reducing computational overhead while maintaining accuracy. The proposed methodology provides a structured approach to deploying ma-chine learning models on FPGAs, demonstrating low-latency inference and energy efficiency, making it suitable for applications in computer vision, ro-botics, and IoT.
IMPLEMENTATION OF NEURAL NETWORKS ON FPGAS FOR REAL-TIME IMAGE PROCESSING
ELIA, PIERANGELO
2023/2024
Abstract
FPGAs offer a highly efficient, parallel, and reconfigurable alternative to CPUs and GPUs for real-time, power-constrained neural network inference, requiring careful hardware optimization. This thesis explores the use of FPGAs for accelerating neural network inference, emphasizing their ad-vantages in real-time and power-constrained applications. It presents the de-sign and implementation of an FPGA-based hardware pipeline for real-time image processing, using a lightweight neural network for color recognition on an Intel DE1-SoC FPGA. The study optimizes the model through quantization techniques, reducing computational overhead while maintaining accuracy. The proposed methodology provides a structured approach to deploying ma-chine learning models on FPGAs, demonstrating low-latency inference and energy efficiency, making it suitable for applications in computer vision, ro-botics, and IoT.| File | Dimensione | Formato | |
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Elia_Pierangelo_Masters_Thesis.pdf
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4.56 MB | Adobe PDF |
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https://hdl.handle.net/20.500.14253/64915